Modern electronic devices, and particularly, integrated circuits, are at risk of damage due to electrostatic discharge (ESD) events. During an ESD event, a voltage (or current) may be provided to one or more terminals of an electronic device that causes the voltage between those terminals to exceed the designed maximum voltage of the device, which could impair subsequent operation of the device. For example, a voltage at a terminal of an electronic device during an ESD event may exceed the breakdown voltage of one or more components of the device, and thereby potentially damage those components. Accordingly, electronic devices include discharge protection circuitry that provides protection from excessive voltages across electrical components during ESD events.
To avoid interfering with normal operation of the device being protected, the discharge protection circuitry is typically designed to turn on and conduct current when the applied voltage exceeds the operating voltage of the device but before the applied voltage exceeds the breakdown voltage of the device. In practice, the discharge protection circuitry may continue to conduct current after being triggered by a transient voltage until the applied voltage is decreased below a particular voltage, referred to as a holding (or snapback) voltage. When the holding voltage is less than the design voltage, discharge protection circuitry may be susceptible to latchup and continue to conduct current at the normal operating voltage, thereby impairing the functionality of the discharge protection circuitry after an ESD event. For example, a transient noise superimposed on a supply voltage may cause the discharge protection circuitry to turn on and continue conducting current after the transient noise is removed.
Multiple instances of protection circuitry may be used to increase the triggering voltage and/or the holding voltage, for example, by “stacking” or otherwise configuring the instances of protection circuitry so that the total triggering and/or holding voltage corresponds to a sum of the triggering and/or holding voltages of the individual instances of protection circuitry. However, due to parasitic capacitances, using multiple instances of protection circuitry undesirably introduces a delay between when the triggering voltage of the stacked protection circuitry is reached and when the voltage propagates through the individual instances of protection circuitry so that the stacked protection circuitry is fully turned on. During this period of time, the ESD voltage may continue to increase and overshoot the breakdown voltage of the circuitry being protected. An individual instance of protection circuitry may be designed for a higher triggering voltage and/or holding voltage without exhibiting the propagation delay associated with multiple stacked instances of protection circuitry; however, such a larger protection circuit typically consumes additional die area beyond that required for stacked protection circuitry providing the same level of protection. Accordingly, it is desirable to reduce the likelihood of voltage overshoot without increasing the die area allocated to the protection circuitry.